1. Field of the Invention
This invention relates to a semiconductor apparatus, and more particularly is used for detecting defects such as cracks and breaks in a semiconductor chip at the time of packaging.
2. Background Art
In recent years, portable devices as typified by mobile phones have been enhanced with various capabilities such as addition of a camera, and the number of components used therefor tends to increase. However, portable devices still continue to be downsized, which increases the demand for using smaller and slimmer components. For this reason, the chip size of semiconductor apparatuses such as power amplifier modules has been reduced, and mount module boards and packages have been made smaller and slimmer. Moreover, the field of packaging techniques has seen an introduction of flip chip bump packaging, which involves smaller packaging area than in using wire bonding.
On the other hand, the above-described power amplifier generates a large amount of heat because of its operation at an extremely high power density, and thus requires close attention to its thermal stability. One of the measures to address this is to improve heat dissipation. One of the technical trends therefor is to reduce the thickness of the chip.
This involves a problem of causing cracks and breaks in a semiconductor chip due to mechanical and thermal stress at the time of packaging such as the mounting and bonding of the semiconductor chip.
Methods of detecting cracks and breaks in a semiconductor chip are disclosed in Japanese Laid-Open Patent Applications 6-244254 (1994) and 6-347509 (1994). In these known arts, as shown in FIG. 10, a conductive pattern is arranged in the chip periphery region. A chip crack will disconnect the conductive pattern. The presence of chip crack is detected by sensing the change of electric characteristics of the pattern. In FIG. 10, a strip-like conductive pattern 102 made of aluminum or silver paste is formed in the periphery region of a semiconductor chip 101 made of compound semiconductor such as a gallium arsenide (GaAs) substrate. The conductive pattern 102 generally circumscribes the semiconductor chip 101. Detecting pads 103 adjacent to each other are connected to both ends of the conductive pattern 102, and configured to detect cracks and breaks in the semiconductor chip 101 by measuring the value of current between the pads.
However, fine cracks (microcracks) may cause only a slight change of electric characteristics because the conductive pattern does not lead to disconnection or the damage to the conductive pattern is not significant. Therefore this method still has a problem that chip cracks cannot be detected reliably.
To solve this problem, a method of using p-n junction is proposed in Japanese Laid-Open Patent Application 6-77300 (1994). This method takes advantage of the fact that a microcrack crossing a p-n junction produces a path of surface current, which changes the electric characteristics of the junction. More specifically, it is suggested that chip cracks, and also microcracks, can be detected by examining leak current under a reverse bias to the p-n junction.
However, the inventor's investigation has revealed a problem that chip cracks cannot be always detected reliably by application of the above approach to a chip of compound semiconductor such as GaAs. More specifically, compound semiconductor as typified by GaAs often incurs a smooth cleavage surface by nature. For this reason, application of the above approach to a chip of compound semiconductor such as GaAs does not always lead to a large leak current. A problem is thus found that chip cracks cannot be detected reliably by examining the electric characteristics of p-n junction.